The present invention relates to a polygon-filling apparatus, and more particularly to a polygon-filling apparatus having a linear interpolation unit for linearly interpolating two sides of a polygon selected based on coordinates data supplied from a host computer, and a linear drawing unit for generating linear drawing data based on the linear-interpolation data.
Usually, a graphic display apparatus indispensably requires a polygon-filling function, and therefore incorporates a polygon-filling apparatus which, as shown in FIG. 5, has linear interpolation units each including a plurality of division circuits and addition circuits, and a linear drawing unit for linearly drawing data obtained by the linear interpolation units.
More specifically, each of the linear interpolation units includes total eight division circuits for interpolation of two sides in x-, y-, z- and I-directions, respectively, and eight addition circuits to which output data from the division circuits are entered, respectively, such that linear interpolation of both sides in x-, y-, z- and I-directions are achieved simultaneously.
The linear drawing unit includes three division circuits to which data obtained by each of the linear interpolation units are entered, and addition circuits to which output data from the division circuits are entered, respectively. The linear drawing unit is adapted to generate a number of pixel data corresponding to a line segment to be drawn based on interpolation data of each side obtained by each of the linear interpolation units, and such pixel data are supplied to a drawing memory.
Accordingly, the linear interpolation operation for two sides can be carried out at a high speed, after which there can be generated a number of pixel data corresponding to line segments to be drawn based on the interpolation data.
To achieve a texture mapping function, there can be added linear interpolation units and a linear drawing unit for a texture plane. To achieve a sectioning function, there can be added a section boundary value interpolation unit for each of the linear interpolation units.
In the polygon-filling apparatus having the arrangement above-mentioned, the linear interpolation units are formed by a number of division circuits and addition circuits, thus presenting the problem that the arrangement is complicated. Further, the frequency in use of such complicated linear interpolation units is considerably less than that of the linear drawing units.
More specifically, it is now supposed that one polygon is, for example, a regular square having 20.times.20 picture elements. To process one polygon, in the linear interpolation units average 25 additions and 1 to 2 divisions are required, whereas in the linear drawing unit, 400 additions and average 25 divisions are required. Thus, the frequency in use of the linear interpolation units is considerably less than that of the linear drawing unit. In spite of such decreased frequency in use, the linear interpolation units require a number of division circuits and a number of addition circuits. This presents a problem of very low working efficiency of the division circuits and the addition circuits.
In the linear interpolation units, an addition operation is carried out in the addition circuits based on data supplied from the division circuits, after which interpolation data thus obtained are transmitted to the linear drawing unit. These addition operation and interpolation data transmission operation are successively carried out serially, as shown in FIG. 6. More specifically, one operation cycle of the addition circuits in the linear interpolation units is complete when, after the adding operation of every addition circuit has been carried out (See Time T0), interpolation data of x, y, z and I for two sides are successively transmitted (See Time T1 to T8), and division start instruction data for the linear drawing unit are finally transmitted (See Time T9).
Accordingly, when the total time for the addition operation and the addition result transmission operation is set, for example, to 1 .mu.sec., the time for the addition operation is 50 nsec., while the time for the addition result transmission operation is 100 nsec., so that the addition circuits are not operated at all in the remaining time of 850 nsec. That is, even though interpolation data of x, y, z and I for two sides have been obtained substantially at the same time, the addition circuits are not operated at all in a relatively long period of time, as above-mentioned. Therefore, the processing time cannot be shortened so much as a whole. Accordingly, even though a number of addition circuits are used such that all interpolation data are obtained substantially at the same time, this merely makes the arrangement complicated with considerable improvements in processing speed.
It is also considered to concurrently transmit interpolation data obtained. This creates the problem that the number of parts to be mounted is considerably increased. Further, even though provision is made so as to achieve a concurrent transmission, another problem is created. That is, a division number obtained based on the starting and terminal points of x- and y-coordinates, is used for a denominator in the division circuit, and this division number is used for obtaining linear drawing data of z- and I-coordinates. Accordingly, a changeover gate is required to supply division number data and interpolation data from the linear interpolation units. Therefore, even though provision is made such that all interpolation data are transmitted concurrently, the processing time cannot be shortened so much and the problem of considerable increase in the number of mounted parts is rather prominent.
This problem is particularly apparent when a texture mapping processing or a sectioning processing is carried out in addition to the polygon-filling operation.